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HY5DU283222AQP
128M(4Mx32) GDDR SDRAM
HY5DU283222AQP
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / Jan. 2005 1
HY5DU283222AQP
Revision History
Revision No. 0.1 Defined target Spec. History Draft Date Jan. 2005 Remark
Rev. 0.1 / Jan. 2005
2
HY5DU283222AQP
CONTENTS
1. 4Mx32 DDR SDRAM Brief Information ------------------------------------------------------------------- 4 1.1 Description 1.2 Feature 1.3 Ordering Information 2. Pin & PKG Information --------------------------------------------------------------------------------------- 5 2.1 Pin Configuration 2.2 Pin Description 2.3 PKG Physical Dimension 3. Functional Block Diagram ----------------------------------------------------------------------------------- 8 4. Command Truth Table ---------------------------------------------------------------------------------------- 9 4.1 Simplified Command Truth Table 4.2 Write Mask Truth Table 4.3 Operation Command Truth Table 4.4 CKE Function Truth Table 5. Function Description ---------------------------------------------------------------------------------------- 16 5.1 Simplified State Diagram 5.2 Power up sequence and Device Initialization 5.3 MRS/EMRS definition 5.4 Device Operation 6. Absolute Maximum Rating -------------------------------------------------------------------------------- 34 7. DC Operating Condition ------------------------------------------------------------------------------------- 34 8. DC Characteristics -------------------------------------------------------------------------------------------- 35 9. AC Operating Test Condition ------------------------------------------------------------------------------ 36 10. AC Characteristics ------------------------------------------------------------------------------------------ 37 11. Input /Output Capacitance & Output Load Circuit ---------------------------------------------- 39 12. Timing Diagram --------------------------------------------------------------------------------------------- 40
Rev. 0.1 / Jan. 2005
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128Mb (4Mx32) Double Data Rate SDRAM
DESCRIPTION
HY5DU283222AQP
The Hynix HY5DU283222 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth. The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.
FEATURES
* * * * * * * VDD, VDDQ = 2.5V 5% All inputs and outputs are compatible with SSTL_2 interface JEDEC standard 20mm x 14mm 100pin LQFP with 0.65mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe * * * * * * * * * All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Write mask byte controls by DM (DM0 ~ DM3) Programmable CAS Latency 3 and 4 supported Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode Internal 4 bank operations with single pulsed RAS tRAS Lock-Out function supported Auto refresh and self refresh supported 4096 refresh cycles / 32ms Half strength and Matched Impedance driver option controlled by EMRS
*
ORDERING INFORMATION
Part No. HY5DU283222AQP-33 HY5DU283222AQP-36 HY5DU283222AQP-4 HY5DU283222AQP-5 VDD/VDDQ = 2.5V Power Supply Clock Frequency 300MHz 275MHz 250MHz 200MHz Max Data Rate 600Mbps/pin 550Mbps/pin 500Mbps/pin 400Mbps/pin SSTL_2 20mm x 14mm 100pin LQFP interface Package
Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free material. We'll add "P" character after "Q" for Lead Free product. For example, the part number of 300MHz Lead Free product is HY5DU283222AQP-33.
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HY5DU283222AQP
PIN CONFIGURATION
VDDQ
VDDQ
DQ31
DQ30
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DM0 DM2 /WE /CAS /RAS /CS BA0 BA1
100
81
DQ29
VSSQ
VSSQ
VSSQ
DQS
DQ2
DQ1
DQ0
VDD
VSS
NC
NC
NC
NC
NC
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
TOP VIEW
20mm x 14mm 100 Pin QFP 0.65mm Pitch
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 46 47 48 49 50
DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ VREF DM3 DM1 CLK /CLK CKE NC A8/AP
37
38
39
40
41
42
43
44
45 A9
VSS
A4
A5
A6
A0
A1
A2
A3
A10
VDD
A11
NC
NC
NC
NC
NC
NC
ROW and COLUMN ADDRESS TABLE
Items
Organization Row Address Column Address Bank Address Auto Precharge Flag Refresh
NC
4Mx32
1M x 32 x 4banks A0 ~ A11 A0 ~ A7 BA0, BA1 A8 4K
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HY5DU283222AQP
PIN DESCRIPTION
PIN CK, /CK TYPE Input DESCRIPTION Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is applied. Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A8 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered. Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the data on DQ24-Q31. Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. Used to capture write data. Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection.
CKE
Input
/CS
Input
BA0, BA1
Input
A0 ~ A11
Input
/RAS, /CAS, /WE
Input
DM0 ~ DM3
Input
DQS DQ0 ~ DQ31 VDD/VSS VDDQ/VSSQ VREF NC
I/O I/O Supply Supply Supply NC
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HY5DU283222AQP
PACKAGE INFORMATION
20mm x 14mm 100pin Low Quad Flat Package
22.10(0.870) 21.90(0.862) 20.10(0.791) 19.90(0.783)
Unit:mm(inch)
1.60(0.063) 1.45(0.057) Base Plane
14.10(0.555) 13.90(0.547)
16.10(0.634) 15.90(0.626)
Detail A
0.15(0.006) 0.05(0.002) 0~7 Deg
Gauge Line 0.20(0.008) 0.09(0.004) 0.75(0.029) 0.50(0.020) 0.66(0.026) 0.45(0.018) 1.00(0.0394)REF
0.65 (0.026)TYP
Seating Plane 0.38(0.015) 0.22(0.009)
0.080 (0.003)
Detail A
All dimension in mm (inches). Notation is
MAX or typical. MIN
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HY5DU283222AQP
FUNCTIONAL BLOCK DIAGRAM
4Banks x 1Mbit x 32 I/O Double Data Rate Synchronous DRAM
Write Data Register 2-bit Prefetch Unit 64 CLK /CLK CKE /CS /RAS /CAS /WE DM(0~3) Bank Control Command Decoder 1Mx32/Bank0 Sense AMP 1Mx32 /Bank1 1Mx32 /Bank2 1Mx32 /Bank3 Mode Register Row Decoder 64
32
Input Buffer
DS
2-bit Prefetch Unit
Output Buffer
32
DQ[0:31]
Column Decoder
A0-11 BA0,BA1
Address Buffer
DQS Column Address Counter CLK_DLL DS Data Strobe Transmitter Data Strobe Receiver
CLK, /CLK
DLL Block
Mode Register
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HY5DU283222AQP
SIMPLIFIED COMMAND TRUTH TABLE
Command Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit CKEn-1 H H H H H CKEn X X X X X CS L L H L L L RAS L L X H L H CAS L L X H H L WE L L X H H H CA RA L H L H H L X X
ADDR
A8/ AP OP code OP code X
BA
Note 1,2 1,2 1
V V
1 1 1,3 1 1,4 1,5 1 1 1 1
H
X
L
H
L
L
CA
V X V
H H H H L
X X H L H
L L L L H L H L H L H L
L H L L X H X H X H X V X
H H L L X H X H X H X V
L L H H X H X H X H X V
X
X
1 1
Entry Precharge Power Down Mode Exit
H
L
X
1 1 1 1
L
H
Active Power Down Mode
Entry Exit
H L
L H
X
1 1
( H=Logic High Level, L=Logic Low Level, X=Don't Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note : 1. DM(0~3) states are Don't Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.
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HY5DU283222AQP
WRITE MASK TRUTH TABLE
Function Data Write Data-In Mask CKEn-1 H H CKEn X X CS, RAS, CAS, WE X X DM(0~3) L H
ADDR
A8/ AP X X
BA
Note
1,2 1,2
Note : 1. Write Mask command masks burst write data with reference to DQS(Data Strobes) and it is not related with read data. 2. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the data on DQ24-Q31.
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OPERATION COMMAND TRUTH TABLE - I
Current State /CS H L L L IDLE L L L L L H L L L ROW ACTIVE L L L L L H L L L READ L L L L L H L WRITE L L L Rev. 0.1 / Jan. 2005 /RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H /CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L /WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP Command DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP Action NOP or power down3 NOP or power down3 ILLEGAL4 ILLEGAL4 ILLEGAL4 Row Activation NOP Auto Refresh or Self Refresh5 Mode Register Set NOP NOP ILLEGAL4 Begin read : optional AP6 Begin write : optional AP6 ILLEGAL4 Precharge7 ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end Terminate burst Term burst, new read:optional AP8 ILLEGAL ILLEGAL4 Term burst, precharge ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL4 Term burst, new read:optional AP8 Term burst, new write:optional AP 11
HY5DU283222AQP
OPERATION COMMAND TRUTH TABLE - II
Current State /CS L WRITE L L L H L L READ WITH AUTOPRECHARGE L L L L L L H L L WRITE AUTOPRECHARGE L L L L L L H L L L PRECHARGE L L L L L /RAS L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L /CAS H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L /WE H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L Address BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE Command ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS Action ILLEGAL4 Term burst, precharge ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL ILLEGAL10 ILLEGAL10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL ILLEGAL10 ILLEGAL10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 NOP-Enter IDLE after tRP NOP-Enter IDLE after tRP ILLEGAL4 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,10 NOP-Enter IDLE after tRP ILLEGAL11 ILLEGAL11
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HY5DU283222AQP
OPERATION COMMAND TRUTH TABLE - III
Current State /CS H L L L ROW ACTIVATING L L L L L H L L L WRITE RECOVERING L L L L L H L L WRITE RECOVERING WITH AUTOPRECHARGE L L L L L L H L REFRESHING L L /RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H /CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L /WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP Command DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP Action NOP - Enter ROW ACT after tRCD NOP - Enter ROW ACT after tRCD ILLEGAL4 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,9,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 NOP - Enter ROW ACT after tWR NOP - Enter ROW ACT after tWR ILLEGAL4 ILLEGAL ILLEGAL ILLEGAL4,10 ILLEGAL4,11 ILLEGAL11 ILLEGAL11 NOP - Enter precharge after tDPL NOP - Enter precharge after tDPL ILLEGAL4 ILLEGAL4,8,10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,11 ILLEGAL11 ILLEGAL11 NOP - Enter IDLE after tRC NOP - Enter IDLE after tRC ILLEGAL11 ILLEGAL11
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HY5DU283222AQP
OPERATION COMMAND TRUTH TABLE - IV
Current State /CS L L WRITE L L L H L L L MODE REGISTER ACCESSING L L L L L /RAS H L L L L X H H H H L L L L /CAS L H H L L X H H L L H H L L /WE L H L H L X H L H L H L H L Address BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE Command WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS Action ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 NOP - Enter IDLE after tMRD NOP - Enter IDLE after tMRD ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11
Note : 1. H - Logic High Level, L - Logic Low Level, X - Don't Care, V - Valid Data Input, BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation. 2. All entries assume that CKE was active(high level) during the preceding clock cycle. 3. If both banks are idle and CKE is inactive(low level), then in power down mode. 4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of that bank. 5. If both banks are idle and CKE is inactive(low level), then self refresh mode. 6. Illegal if tRCD is not met. 7. Illegal if tRAS is not met. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Illegal if tRRD is not met. 10. Illegal for single bank, but legal for other banks in multi-bank devices. 11. Illegal for all banks.
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HY5DU283222AQP
CKE FUNCTION TRUTH TABLE
Current State CKEn1 H L L SELF REFRESH1 L L L L H L POWER DOWN2 L L L L L H H H ALL BANKS IDLE4 H H H H H L ANY STATE OTHER THAN ABOVE H H L L CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L /CS X H L L L L X X H L L L L X X L H L L L L L X X X X X /RAS X X H H H L X X X H H H L X X L X H H H L L X X X X X /CAS X X H H L X X X X H H L X X X L X H H L H L X X X X X /WE X X H L X X X X X H L X X X X H X H L X X L X X X X X /ADD X X X X X X X X X X X X X X X X X X X X X X X X X X X Action INVALID Exit self refresh, enter idle after tSREX Exit self refresh, enter idle after tSREX ILLEGAL ILLEGAL ILLEGAL NOP, continue self refresh INVALID Exit power down, enter idle Exit power down, enter idle ILLEGAL ILLEGAL ILLEGAL NOP, continue power down mode See operation command truth table Enter self refresh Exit power down Exit power down ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP See operation command truth table ILLEGAL5 INVALID INVALID
Note : When CKE=L, all DQ and DQS must be in Hi-Z state. 1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command. 2. All command can be stored after 2 clocks from low to high transition of CKE. 3. Illegal if CK is suspended or stopped during the power down mode. 4. Self refresh can be entered only from the all banks idle state. 5. Disabling CK may cause malfunction of any bank which is in active state.
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HY5DU283222AQP
SIMPLIFIED STATE DIAGRAM
MODE REGISTER SET
MRS IDLE
SREF SREX SELF REFRESH
PDEN PDEX POWER DOWN POWER DOWN PDEX PDEN BST BANK ACTIVE ACT AREF AUTO REFRESH
READ WRITE READAP WRITE WRITEAP PRE(PALL) WRITE WITH AUTOPRECHARGE READ READAP WITH AUTOPRECHARGE WRITEAP READ READ
WRITE PRE(PALL) PRE(PALL) PRECHARGE
POWER-UP
Command Input Automatic Sequence
POWER APPLIED
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POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied anytime after VDDQ, but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200us delay prior to applying an executable command. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Register set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation. 1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVCMOS low state. (All the other input pins may be undefined.) * VDD and VDDQ are driven from a single power converter output. * VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation. * VREF tracks VDDQ/2. * A minimum resistance of 42 Ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the input current from the VTT supply into any pin. * If the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must be adhered to during power up. Votage description VDDQ VTT VREF 2. 3. 4. 5. 6. Sequencing After or with VDD After or with VDDQ After or with VDDQ Voltage relationship to avoid latch-up < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V
Start clock and maintain stable clock for a minimum of 200usec. After stable power and clock, apply NOP condition and take CKE high. Issue Extended Mode Register Set (EMRS) to enable DLL. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=High. (An additional 200 cycles(tXSRD) of clock are required for locking DLL) Issue Precharge commands for all banks of the device.
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7. 8. Issue 2 or more Auto Refresh commands. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.
Power-Up Sequence
VDD
VDDQ
tVTD
VTT VREF
/CLK CLK
tIS tIH
CKE
LVCMOS Low Level
CMD
NOP
PRE
EMRS
MRS
NOP
PRE
AREF
MRS
ACT
RD
DM
ADDR
CODE
CODE
CODE
CODE
CODE
A10
CODE
CODE
CODE
CODE
CODE
BA0, BA1
CODE
CODE
CODE
CODE
CODE
DQS
DQ'S
T=200usec tRP tMRD tMRD tRP tRFC tXSRD* Power UP VDD and CK stable Precharge All EMRS Set MRS Set Reset DLL (with A8=H) Precharge All 2 or more Auto Refresh MRS Set (with A8=L) Non-Read Command READ tMRD
* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command
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MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low signals of RAS, CAS, CS, WE and BA0. This command can be issued only when all banks are in idle state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is determined, the information will be held until resetted by another MRS command.
BA1 0
BA0 0
A11
A10 RFU
A9
A8 DR
A7 TM
A6
A5
A4
A3 BT
A2
A1
A0
CAS Latency
Burst Length
BA0 0 1
MRS Type MRS EMRS
A7 0 1
Test Mode Normal Vendor test mode Burst Length A2 A1 A0 Sequential 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved Interleave Reserved 2 4 8 Reserved Reserved Reserved Reserved
A8 0 1
DLL Reset No Yes
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved Reserved 3 4 Reserved Reserved Reserved A3 0 1
0 1 1 1 1
Burst Type Sequential Interleave
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HY5DU283222AQP
BURST DEFINITION
Burst Length 2 Starting Address (A2,A1,A0) XX0 XX1 X00 4 X01 X10 X11 000 001 010 8 011 100 101 110 111 Sequential 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 0, 1, 2, 3, 4, 5, 6, 7 Interleave 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
BURST LENGTH & TYPE
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts. Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definitionon Table
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CAS LATENCY
The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 3 or 4 clocks. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n +m. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
DLL RESET
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before an any command can be issued.
OUTPUT DRIVER IMPEDANCE CONTROL
The HY5DU283222 supports both Half strength driver and Matched impedance driver, intended for lighter load and/or point-to-point environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2, Class II, and Matched impedance driver, about 30% of Full drive strength.
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EXTENDED MODE REGISTER SET (EMRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low signals of RAS, CAS, CS, WE and BA0. This command can be issued only when all banks are in idle state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is determined, the information will be held until resetted by another MRS command.
BA1 0
BA0 1
A11
A10
A9 RFU*
A8
A7
A6 DS
A5
A4
A3
A2
A1 DS
A0 DLL
RFU*
BA0 0 1
MRS Type MRS EMRS
A0 0 1
DLL enable Enable Diable
A2 0 0 0 0 1 1 1 1
A6 0 0 1 1 0 0 1 1
A1 0 1 0 1 0 1 0 1
Output Driver Impedance Control RFU* Half (60%) RFU* Weak (40%) RFU* Semi Half (50%) RFU* Semi Weak (30%)
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.
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FUNCTION DESCRIPTION
Burst Read and Burst Write
Burst Read and Burst Write commands are initiated as listed in Fig.1. Before the Burst Read command, the bank must be activated earlier. After /RAS to /CAS delay (tRCD), read operation starts. DDR SDRAM has been implemented with Data Strobe signal (DQS) which toggles high and low during burst with the same frequency as clock (CLK, /CLK). After CAS Latency (CL) which is defined as the interval between command clock and the first rising edge of the DQS, read data is launched onto data pin (DQ) with reference to DQS signal edge. Burst Write command in another bank can be given with having activated that bank where /RAS to /RAS delay (tRRD) is satisfied. Write data is also referenced and aligned to the DQS signal sent from the memory controller. Since all read operation bursts data out at both the rising and the falling of the DQS, double data bandwidth can be achieved, also for write data. Fig.1. Burst Read and Burst Write
/CLK CLK CKE /CS
tRRD
tRCD Row_A Col_A
CL Row_B Col_B
RA, CA AP BA /RAS /CAS /WE DM DQS DQ
Row_A Bank 0
No PCG Bank 0
Row_B Bank 1
AutoPCG Bank 1
Activate Bank 0
Read Bank 0
Activate Bank 1
Write Bank 1 w/ Autopcg
A0 A1 A2 A3
B0 B1 B2 B3
Burst length =4, CAS latency =2
Bank 0 Data-out
Bank 1 Data-in
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Burst Read followed by Burst Read
Back to back read operation in the same or different bank is possible as shown in Fig.2. Following first Read command, consecutive Read command can be initiated after BL/2 ticks of clock. In other words, minimum earliest possible Read command that does note interrupt the previous read data, can be issued after BL/2 clock is met. When Read(B) data out starts, data strobe signal does not transit to Hi-Z but toggle high and low for Read(B) data. Fig.2. Burst Read followed by Burst Read
/C L K CLK
CMD
R E AD (A)
R E AD (B )
DQS
DQ
A0
A1
A2
A3
B0
B1
B2
B3
B urst length =4, C A S latency =2
R EAD (B) data out starts
Burst Write followed by Burst Write
Back to back write operation in the same or different bank is possible as shown in Fig.3. Following first Write command, consecutive Write command can be initiated after BL/2 ticks of clock. In other words, minimum earliest possible Write command that does note interrupt the previous write data, can be issued after BL/2 clock is met. When Write(B) data in starts, data strobe signal does not transit to Hi-Z but toggle high and low for Write(B) data. Though the timing shown in Fig.3. is based on tDQSS=0.75*tCK, minimum number of clock of BL/2 for back to back write can be applied when tDQSS=1.25*tCK. Fig.3. Burst Write followed by Burst Write
/CLK CLK
CMD
WRITE (A) tDQSS
WRITE (B)
DQS
DQ
A0
A1
A2
A3
B0
B1
B2
B3
Burst length =4, CAS latency =2
W RITE(B) data in starts
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Burst Read followed by Burst Write
Back to back read followed by write operation in the same or different bank is possible as shown in Fig.4. Following first Read command, consecutive Write command can be initiated after RU{CL+BL/2} ticks of clock. (RU=Round Up for half cycle of CAS latency, such as 1.5 and 2.5). In other words, minimum earlist possible Write command that does not interrupt the previous read data can be issued after RU{CL+BL/2} clock is met. Fig.4. Burst Read followed by Burst Write
/CLK CLK
CMD
R E AD (A)
W R ITE (B )
DQS
DQ
A0
A1
A2
A3
B0
B1
B2
B3
B urst length =4, C A S latency =2
Burst Write followed by Burst Read
Back to back write followed by read operation in the same or different bank is possible as shown in Fig.5. Following first Write command, consecutive Read command can be initiated after (BL/2+1+tDRL) ticks of clock. In other words, minimum earlist possible Read command that does not interrupt the previous write data can be issued after (BL/ 2+1+tDRL) clock is met. Fig.5. Burst Write followed by Burst Read
/CLK CLK
CMD
WRITE (A)
READ (B) tDRL
tDRL is counted with respect to CLK rising edge after last falling edge of DQS and DQ data has elapsed
DQS
DQ
A0
A1
A2
A3
B0
B1
B2
B3
Burst length =4, CAS latency =2
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Burst Read terminated by another Burst Read
Read command terminates the previous Read command and the data is available after CAS latency for the new command. Minimum delay from a Read command to next Read command is determined by /CAS to /CAS delay (tCCD). Timing diagram is shown in Fig.6. Fig.6. Burst Read terminated by another Burst Read
/C LK C LK
tC C D
CMD
R E AD (A)
R E AD (B )
DQS
DQ
A0
A1
B0
B1
B2
B3
B urst length =4, C A S latency =2
R ead(A) is term inated and R ead(B ) data out starts
Burst Write terminated by another Burst Write
Write command terminates the previous Write command and the data is available after CAS latency for the new command. Fastest Write command to next Write command is determined by /CAS to /CAS delay (tCCD). Timing diagram is shown in Fig.7. Fig.7. Burst Write terminated by another Burst Write
/C LK C LK
tC C D
CMD
W R ITE (A) W R ITE (B )
DQ S
DQ
A0
A1
B0
B1
B2
B3
B urst length =4, CA S latency =2
W rite(A) is term inated and W rite(B) data in starts
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Burst Read terminated by another Burst Write
Write command terminates the previous Read command with the insertion of Burst Stop command that disables the previous Read command. The Burst Stop command interrupts bursting read data and data strobe signal with the same latency as CAS Latency (CL). The minimum delay for Write command after Burst Stop command is RU{CL} clocks irrespective BL. The Burst Stop command is valid for Read command only. Fig.8. Burst Read terminated by another Burst Write
/CLK CLK
tCCD
CMD
READ (A)
BST (A)
W RITE (B) Burst DQS & DQ stop
DQ S
DQ
A0
A1
B0
B1
B2
B3
Burst length =4, CAS latency =2
W rite data starts
Burst Write terminated by another Burst Read
Read command terminates the previous Write command and the new burst read starts as shown in Fig.9. The minimum write to read command delay is 2 clock cycle irrespective of CL and BL. If input write data is masked by the Read command, DQ and DQS input are ignored by the DDR SDRAM. It is illegal for a Read command to interrupt a Write with autoprecharge command. Fig.9. Burst Write terminated by another Burst Read
/CLK CLK
CMD
WRITE (A)
READ (B)
DQS
Masked
DQ
A0
A1
A2
A3
B0
B1
B2
B3
DM
Burst length =4, CAS latency =2
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Burst Read with Autoprecharge
If a Read with Autoprecharge command is detected by memory component in CLK(n), then there will be no commands presented to this bank until CLK(n+BL/2+tRP). Internal precharging action will happen in CLK(n+BL/2). Fig.10. Burst Read with Autoprecharge
/C L K CLK
B L/2 + tR P
CMD
R E AD (A ) w / Autop cg
AC T
DQS
E arly term ination is illegal here
DQ
A0
A1
A2
A3
B urst length =4, C A S latency =2
Burst Write with Autoprecharge
If a Write with Autoprecharge command is detected by memory component in CLK(n), then there will be no commands presented to this bank until CLK(n+BL/2+1+tDPL+tRP). Last Data in to Precharge delay time (tDPL) is needed to guarantee the last data has been written. tDPL is measured with respect to rising edge of clock where last falling edge of data strobe (DQS) and DQ data has elapsed. Internal precharging action will happen in CLK(n+BL/2+1+tWR) as shown in Fig.11. Fig.11. Burst Write with Autoprecharge
/CLK CLK
tD P L tR P AC T
CMD
W R IT E (A) w / Au to p cg
DQS
DQ
A0
A1
A2
A3
B urst length =4, C A S latency =2
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Precharge command after Burst Read
The earlist Precharge command can be issued after Read command without the loss of data is BL/2 clocks. The Precharge command can be given as soon as tRAS time is met. Fig.12 shows the earlist possible Precharge command can be issued for CL=2 and BL=4. Fig.12. Precharge command after Burst Read
/C LK C LK
tRP
CM D
R E AD (A)
PR EC HG
AC T
DQ S
DQ
A0
A1
A2
A3
Earliest precharge tim e without losing read data
Burst length =4, C AS latency =2
Precharge command after Burst Write
The earliest Precharge command can be issued after Write command without the loss of data is (BL/2+1+tDPL) ticks of clocks. The Precharge command can be given as soon as tRAS time is met. Fig.13 shows the earliest possible Precharge command can be issued for CL=2 and BL=4. Fig.13. Precharge command after Burst Write
/CLK CLK
tRP
CMD
W RITE (A)
PRECHG tDPL
ACT
DQS
Issuing precharge here allows completion of entire burst write
DQ
A0
A1
A2
A3
tDPL is counted with respect to CLK rising edge after last falling edge of DQS and DQ data has elapsed
Burst length =4, CAS latency =2
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Precharge termination of Burst Read
The Burst Read (with no Autoprecharge) can be terminated earlier using a Precharge command as shown in Fig.14. This terminates read data when the remaining elements are not needed. It allows starting precharge early. The Precharge command can be issued any time after Burst Read command when tRAS time is met. Activation or other commands can be initiated after tRP time. Fig.14. Precharge termination of Burst Read
/CLK CLK
tRP
CMD
READ (A)
PRECHG
ACT
DQS
DQ
A0
A1
Precharge time can be issued here with tRASmin being met
Burst length =4, CAS latency =2
Precharge termination of Burst Write
The Burst Write (with no Autoprecharge) can be terminated earlier using a Precharge command along with the Write Mask (DM) as shown in Fig.15. This terminates write data when the remaining elements are not needed. It allows starting precharge early. Precharge command can be issued after Last Data in to Precharge delay time (tDPL). tDPL is measured with respect to rising edge of clock where last falling edge of data strobe (DQS) and DQ data has elapsed. DM should be used to mask the remaining data (A2 and A3 for this case). tRAS time must be met to issue the Precharge command. Fig.15. Precharge termination of Burst Write
/CLK CLK
CMD
W RITE (A) tDQ SS
PREC HG tDPL tR P
AC T
DQ S
M asked tDPL is counted with respect to CLK rising edge after last falling edge of DQ S and DQ data has elapsed
DQ
A0
A1
A2
A3
DM
W rite burst is term inated early. DM is asserted to prevent locations of A2 and A3
Burst length =4, CAS latency =2
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DM masking (Write)
DM command masks burst write data with reference to data strobe signal and it is not related with read data. DM command can be initiated at both the rising edge and the falling edge of the DQS. DM latency for write operation is zero. For x16 data I/O, DDR SDRAM is equipped with LDM and UDM which control lower byte (DQ0~DQ7) and upper byte (DQ8~DQ15) respectively. Fig.16. DM masking (Write)
/CLK CLK
CMD
WRITE (A) tDQSS
DQS
Masked Masked A1 A2 A3
DQ
A0
DM
DM can mask write data with reference to DQS DM write latency = 0
Burst length =4, CAS latency =2
Burst Stop command (Read)
When /CS=L, /RAS=H, /CAS=H and /WE=L, DDR SDRAM enter into Burst Stop mode, which bursts stop read data and data strobe signal with reference to clock signal. BST command can be initiated at the rising edge of the clock as other commands do. BST command is valid for read operation only. BST latency for read operation is the same as CL. Fig.17. Burst Stop command (Read)
/C L K CLK
CMD
R E AD (A )
B S T (A) B u rst D Q S & D Q sto p
DQS
DQ
A0
A1
B urst length =4, C A S latency =2
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Auto Refresh and Precharge All command
When /CS=L, /RAS=L, /CAS=L and /WE=H, DDR SDRAM enter into Auto Refresh mode, which executes refresh operation with internal address increment. AREF command can be initiated at the rising edge of the clock as other commands do. Before entering Auto Refresh mode, all banks must be in a precharge state and AREF command can be issued after tRP period from Precharge All command. Fig.18. Auto Refresh and Precharge All command
/CLK CLK
tRP
tRC = tRAS + tRP
CMD
PRECHG Precharge all
AUTOREF
ACT
DQS DQ
Hi-Z
Held High
CKE
Self Refresh Entry and Exit
When CKE=L, /CS=L, /RAS=L, /CAS=L and /WE=H, DDR SDRAM enter into Self Refresh mode, which executes self refresh operation with internal address increment. Before issuing Self Refresh command, all banks must be in a precharge state and CKE must be low. SREF command can be initiated at the rising edge of the clock as other commands do. Because the clock buffer and internal DLL circuit are disabled during self refresh state, Self Refresh Exit (SREX) should guarantee the stable input clock. Therefore, a minimum of 200 cycles of stable input clock, where CKE is held high, is required to lock the internal DLL circuit of DDR SDRAM. A minimum tPDEX (Power Down Exit Time) must be met before entering SREX command. Fig.19. Self Refresh Entry and Exit
/CLK CLK
CM D
PR EC H G Precharge all
SR EF
D ESL
SR EX
AC T
M in. 200 clock cycles tXSC
CKE
tPD EXm in
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Power Down mode
A Power Down mode can be achieved by asserting CKE=L as shown in Fig.20. There are two kinds of Power Down mode: 1. Active and 2. Precharge Power Down mode. The device must be in idle state and all banks must be closed before CKE assertion in Precharge Power Down mode. Active Power Down mode can be initiated in row active state. The device will exit Power Down mode when CKE is sampled high at the rising edge of the clock. Fig.20. Power Down mode
/C LK C LK
CMD
PR EC H G
PD EN
PD EX
AC T
CK E
N ew com m and can be issued after Power D own exit
Precharge Power Down M ode
CKE function
Since clock suspend mode in SDR SDRAM cannot be used in DDR SDRAM, it is illegal to issue CKE=L during read or write burst. Fig.21. CKE function
/CLK CLK
CMD
READ (A)
WRITE (B)
DQS
DQ
A0
A1
A2
A3
B0
B1
B2
B3
CKE
Transition of CKE(to Low) is illegal during Burst Read and W rite
Burst length =4, CAS latency =2
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ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Output Short Circuit Current Power Dissipation Soldering Temperature Time
Symbol
TA TSTG VIN, VOUT VDD VDDQ IOS PD TSOLDER
Rating
0 ~ 70 -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0.5 ~ 3.6 50 1 260 10
o
Unit
oC oC
V V V mA W C sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
Parameter
Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Termination Voltage Reference Voltage
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Symbol
VDD VDDQ VIH VIL VTT VREF
Min
2.375 2.375 VREF + 0.15 -0.3 VREF - 0.04 0.49*VDDQ
Typ.
2.5 2.5 VREF 0.5*VDDQ
Max
2.625 2.625 VDDQ + 0.3 VREF - 0.15 VREF + 0.04 0.51*VDDQ
Unit
V V V V V V
Note
1
2
3
Note : 1. VDDQ must not exceed the level of VDD. 2. VIL (min) is acceptable -1.5V AC pulse width with 5ns of duration. 3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to peak noise on VREF may not exceed 2% of the dc value.
DC CHARACTERISTICS I
Parameter
Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Symbol
ILI ILO VOH VOL
Min.
-5 -5 VTT + 0.76 -
Max
5 5 VTT - 0.76
Unit
uA uA V V
Note
1 2 IOH = -15.2mA IOL = +15.2mA
Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V. 2. DOUT is disabled, VOUT=0 to 2.7V Rev. 0.1 / Jan. 2005 34
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DC CHARACTERISTICS II
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Speed Parameter Symbol Test Condition 33 Burst length=4, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = min CKE VIH(min), CS VIH(min), tCK = min, Input signals are changed one time during 2clks CKE VIL(max), tCK = min CKE VIH(min), CS VIH(min), tCK = min, Input signals are changed one time during 2clks tCK tCK(min), IOL=0mA All banks active tRC tRFC(min), All banks active CKE 0.2V 36 4 5 Unit Note
Operating Current Precharge Standby Current in Power Down Mode Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non Power Down Mode Burst Mode Operating Current Auto Refresh Current Self Refresh Current
ICC1
240
210
mA
1
ICC2P
30
20
mA
ICC2N
90
80
mA
ICC3P
35
25
mA
ICC3N
130
100
mA
ICC4
450
370
mA
1
ICC5 ICC6
270 3
mA mA
1,2
Note : 1. ICC1, ICC4 and ICC5 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.
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AC OPERATING CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.45 VREF - 0.45 VDDQ + 0.6 0.5*VDDQ+0.2 Max Unit V V V V 1 2 Note
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter Reference Voltage Termination Voltage AC Input High Level Voltage (VIH, min) AC Input Low Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS) Output Load Capacitance for Access Time Measurement (CL) Value VDDQ x 0.5 VDDQ x 0.5 VREF + 0.45 VREF - 0.45 VREF VTT 1.5 1 50 25 TBD Unit V V V V V V V V/ns pF
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AC Overshoot/Undershoot specifications for Address and Command pins
Parameter Maximum peak amplitude allowwed for overshoot Maximum peak amplitude allowwed for undershoot The area between the overshoot signal and VDD must be less than or equal to(See below Fig) The area between the overshoot signal and GND must be less than or equal to(See below Fig) Specifications 1.5 V 1.5 V 4.5 V-nS 4.5 V-nS
+5 Volt (v) + 4 +3 +2 +1 0 -1
Max. Amplitude = 1.5v
VDD
Ground
Max. area = 4.5v-nS
-2 -3 0 1 2 3 Time(nS) 4 5 6
AC Overshoot/Undershoot specifications for Data, Strobe and Mask Pins
Parameter Maximum peak amplitude allowwed for overshoot Maximum peak amplitude allowwed for undershoot The area between the overshoot signal and VDD must be less than or equal to(See below Fig) The area between the overshoot signal and GND must be less than or equal to(See below Fig)
+5 Volt (v) + 4 +3 +2 +1 0 -1
Specifications 1.2 V 1.2 V 2.4 V-nS 2.4 V-nS
Max. Amplitude = 1.2v
VDD
Ground
Max. area = 2.4 v-nS
-2 -3 0 1 2 3 4 Time(nS) 5 6
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AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Row Address to Column Address Delay for Read Row Address to Column Address Delay for Write Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Last Data-In to Precharge Delay Time (Write Recovery Time : tWR) Last Data-In to Read Command Auto Precharge Write Recovery + Precharge Time System Clock Cycle Time Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS Clock Half Period Data Hold Skew Factor Input Setup Time Input Hold Time Write DQS High Level Width Write DQS Low Level Width CL = 4 CL = 3 Symbol tRC tRFC tRAS tRCDRD tRCDWR tRRD tCCD tRP tDPL tDRL tDAL 33 Min 49.5 56.1 29.7 6 2 3 1 6 3 2 9 3.3 0.45 0.45 0.7 0.7 0.4
tHPtQHS
36 Max 6 0.55 0.55 0.6 0.6 Min 50.4 57.6 32.4 5 2 3 1 5 3 2 8 3.6 0.45 0.45 0.7 0.7 0.4
tHPtQHS
4 Max 6 0.55 0.55 0.6 0.6 Min 52 60 32 5 2 3 1 5 3 2 8 4 0.45 0.45 0.7 0.7 0.4
tHPtQHS
5 Max 10 0.55 0.55 0.6 0.6 Min 50 60 35 4 2 3 1 4 2 2 6 5 0.45 0.45 0.7 0.7 0.4
tHPtQHS
Max 10 0.55 0.55 0.6 0.6
Unit Note
ns ns ns CK CK CK CK CK CK CK CK ns ns CK CK ns ns ns ns ns ns ns ns CK CK 1,6 1,5 6 2 2
tCK tCH tCL tAC tDQSCK tDQSQ tQH tHP tQHS tIS tIH tDQSH tDQSL
tCH/L min 0.45 0.75 0.75 0.4 0.4
tCH/L min 0.45 0.75 0.75 0.4 0.4
tCH/L min 0.45 0.75 0.75 0.4 0.4
tCH/L min 0.45 0.75 0.75 0.4 0.4
Rev. 0.1 / Jan. 2005
38
HY5DU283222AQP
Parameter Clock to First Rising edge of DQS-In Data-In Setup Time to DQS-In (DQ & DM) Symbol tDQSS tDS 33 Min 0.75 0.4 0.4 0.2 0.2 0.8 0.4 0 1.5 0.4 2 200 Max 1.25 1.1 0.6 0.8 7.8 Min 0.75 0.4 0.4 0.2 0.2 0.8 0.4 0 1.5 0.4 2 200 36 Max 1.25 1.1 0.6 0.8 7.8 Min 0.75 0.4 0.4 0.2 0.2 0.8 0.4 0 1.5 0.4 2 200 4 Max 1.25 1.1 0.6 0.8 7.8 Min 0.75 0.45 0.45 0.2 0.2 0.8 0.4 0 1.5 0.4 2 200 5 Max 1.25 1.1 0.6 0.8 7.8
Unit Note
CK ns ns CK CK CK CK ns ns CK CK CK us 4 3 3
Data-In Hold Time to DQS-In (DQ & DM) tDH DQS falling edge to CK setup time DQS falling edge hold time from CK Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any Execute Command Average Periodic Refresh Interval tDSS tDSH tRPRE tRPST tWPRES tWPREH tWPST tMRD tXSC tREFI
Note :
1. 2. 3. 4. 5. 6. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM(0~3). Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic.
7.
Rev. 0.1 / Jan. 2005
39
HY5DU283222AQP
CAPACITANCE (TA=25oC, f=1MHz )
Parameter Input Clock Capacitance Input Capacitance Input / Output Capacitance CK, CK All other input-only pins DQ, DQS, DM Pin Symbol CCK CIN CIO Min 1.7 1.7 3.7 Max 2.7 2.7 4.7 Unit pF pF pF
Note : 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
VTT
VTT
RT=50
RT=50
Output RS=25 Zo=50 VREF
CL=30pF
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HY5DU283222AQP
Timing Diagram
Data Input (Write) Timing (BL=4)
tDQSL DQS tDQSH
tDH tDS DQ DI n
tDH tDS DM
DI n = Data in for column n 3 subsequent elements of data in are applied in the programmed order following DI n
Don't care
Data Output (Read) Timing (BL=4)
/CK CK tDQSCK max DQS tQH
DQ
DQ n
tDQSQ and tQH are only shown once, and are shown referenced to different edges of DQS, only for clarify of illustration. tDQSQ and tQH both apply to each of the four relevant edges of DQS. tQHmin = tHPmin - X where ; tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL) X consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.
Rev. 0.1 / Jan. 2005
41
HY5DU283222AQP
Power Down Mode
tCK
tCH
tCL
CK
tIS tIH tIS tIS
CKE
tIS
tIH
COMMAND
VALID*
~ ~
~ ~
~ ~
/CK
NOP
NOP
VALID
tIS
tIH
ADDR
VALID
~ ~
VALID
DQS
DQ
DM
~ ~
~ ~
~ ~
Enter Power-Down Mode
Exit Power-Down Mode
Don't Care
No column accesses are allowed to be in progress at the time Power-Down is entered. * = If this command is a PRECHARGE (or if the device is already in the idle state) then the Power-Down mode shown is Precharge Power Down. If this command is an ACTIVE (or if at least one row is already active) then the Power-Down mode shown is Active Power Down.
Rev. 0.1 / Jan. 2005
42
HY5DU283222AQP
Auto Refresh Mode
tCK tCH tCL
/CK CK
tIS tIH
~ ~
CKE
tIS tIH
~ ~
~ ~
VALID
VALID
COMMAND
~ ~
~ ~
~ ~
NOP
PRE
NOP
NOP
AR
NOP
AR
NOP
NOP
ACT
~ ~
ADDR
~ ~
RA
AP
ONE BANK tIS tIH
~ ~
~ ~
ALL BANKS
RA
BA0,BA1
~ ~
~ ~
*Bank(s)
BA
DQS
~ ~
DQ
~ ~
DM
tRP
~ ~
~ ~
tRFC tRFC
~ ~
~ ~
Don't Care
* = " Don't Care ", if AP is High at this point ; AP must be High if more than one bank is active ( i.e., must precharge all active banks) PRE = Precharge, ACT = Active, RA = Row Address, BA = Bank Address, AR = Autorefresh. NOP commands are shown for ease of illustration ; other valid commands may be possible at these times. DM, DQ and DQS signals are all "Don't Care" / High-Z for operation shown.
Rev. 0.1 / Jan. 2005
43
HY5DU283222AQP
Self Refresh Mode
tCK
tCH
tCL
clock must be stable before exiting Self Refresh mode
~ ~
/CK CK
tIS tIH tIS
tIS
CKE
tIS
tIH
~ ~
~ ~
COMMAND
NOP
AR
NOP
~ ~
VALID tIS tIH
~ ~
ADDR
~ ~
tXSNR/ tXSRD** Exit Self Refresh Mode
~ ~
VALID
~ ~
DQS
~ ~
DQ
~ ~
DM
tRP* Enter Self Refresh Mode
~ ~
Don't Care
* = Device must be in the "All banks idle" state prior to entering Self Refresh mode ** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK) are required before a READ command can be applied.
Rev. 0.1 / Jan. 2005
~ ~
~ ~
~ ~
44
HY5DU283222AQP
Read Without Auto Precharge
tCK
tCH
tCL
/ /CK CK
tIS tIH tIH VALID tIS tIH READ tIS tIH RA NOP PRE NOP NOP ACT NOP NOP NOP VALID VALID
CKE
CMD
NOP
CA, RA
Col n
RA
tIS tIH ALL BANKS
RA
AP
tIS tIH ONE BANK
RA
BA0,BA1
Bank x CL = 2
*Bank x tRP
Bank x
DM
Case 1: tAC/tDQSCK=min
tRPRE tDQSCK min tRPST
DQS
tLZ min tHZ min Do n tLZ min tAC min
DQ
Case 2: tAC/tDQSCK=max
tRPRE tDQSCK max tRPST
DQS
tLZ max tHZ max Do n tLZ max tAC max
DQ
Don't Care DO n = Data Out from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n DIS AP = Disable Autoprecharge * = "Don't Care", if AP is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration ; other commands may be valid at these times
Rev. 0.1 / Jan. 2005
45
HY5DU283222AQP
Read With Auto Precharge
tCK
tCH
tCL
/CK CK CKE
tIS tIH READ tIS tIH RA NOP NOP NOP NOP ACT NOP NOP NOP tIS tIH tIH VALID VALID VALID
CMD
NOP
CA, RA
Col n
RA
EN AP
RA
AP
tIS tIH
RA
BA0,BA1
Bank x CL = 2 tRP
Bank x
DM
Case 1: tAC/tDQSCK=min
tRPRE tDQSCK min tRPST
DQS
tLZ min tHZ min Do n tLZ min tAC min tQPST
DQ
Case 2: tAC/tDQSCK=max
tRPRE
tDQSCK max
tRPST
DQS
tLZ max tHZ max Do n tLZ max tAC max
DQ
Don't Care
DO n = Data Out from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n EN AP = Enable Autoprecharge, ACT = ACTIVE, RA = Row Address NOP commands are shown for ease of illustration ; other commands may be valid at these times
Rev. 0.1 / Jan. 2005
46
HY5DU283222AQP
Bank Read Access
tCK tCH tCL
/CK CK
tIS tIH
CKE
CMD
NOP
ACT tIS tIH
NOP
NOP
NOP
READ
NOP
PRE
NOP
NOP
ACT
RA, CA
RA
Col n
RA
RA
RA All Bank
RA
tIS tIH
AP
tIS
RA tIH DIS AP Bank x tRC tRAS tRCD CL=2 tRP One Bank
RA
BA0,BA1
Bank x
Bank x
Bank x
DM
Case1: tAC/tDQSCK=min DQS
tLZ min tRPRE
tDQSCK min tRPST tHZ min
DQ
tLZ min
DQ n
tAC min
CASE2 : tAC/tDQSCK=max
tDQSCK max
DQS
tLZ max
tRPRE
tRPST tHZ max
DQ
tLZ max
DQ n
tAC max
DQ n = Data out from column n Burst length = 4 in the case shown 3 subsequent elements of Data out are provided in the programmed order following DQ n DIS AP = Disable Autoprecharge * = * " Don't Care", if AP is high at this point PRE = Precharge, ACT=Active, RA=Row Address, BA=Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Note that tRCD > tRCD min so that the same timing applies if Autoprecharge is enabled (in which case tRAS would be limiting)
Don't care
Rev. 0.1 / Jan. 2005
47
HY5DU283222AQP
Write Without Auto Precharge
tCK tCH tCL
/CK CK
tIS tIH Valid
CKE
CMD
NOP
Write tIS tIH
NOP
NOP
NOP
NOP
PRE
NOP
NOP
ACT
RA, CA
Col n
RA
RA
tIS tIH All Bank
RA
AP
DIS AP tIS tIH Bank x tDSH tDQSS tDQSH tWPST tDPL tRP One Bank
RA
BA0,BA1 Case 1 : tDQSS = min DQS
Bank x
BA
tWPRES tDQSL tWPRE
DQ
DI n
DM
Case 2 : tDQSS = max
tDQSS tDQSH
tDSS
tDSS tWPST
DQS
tWPRES tWPRE tDQSL DI n
DQ
DM
DI n = Data in for column n Burst length = 4 in the case shown 3 subsequent elements of Data In are provided in the programmed order following DI n DIS AP = Disable Autoprecharge * = * " Don't Care", if AP is high at this point PRE = Precharge, ACT=Active, RA=Row Address, BA=Bank Address NOP commands are shown for ease of illustration; other valid commands may be possible at these times
Don't care
Rev. 0.1 / Jan. 2005
48
HY5DU283222AQP
Write With Auto Precharge
tCK tCH tCL
/CK CK
tIS tIH VALID VALID VALID
CKE
CMD
NOP
WRITE tIS tIH
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ACT
RA, CA
Col n
RA
RA
EN AP
RA
AP
tIS tIH
RA
BA0,BA1 Case 1 : tDQSS = min DQS
Bank x tDSH tDQSS tDQSH tWPST tDAL
BA
tWPRES tDQSL tWPRE
DQ
DI n
DM
Case 2 : tDQSS = max
tDSS tDQSS tDSS tDQSH tWPST
DQS
tWPRES tWPRE DI n tDQSL
DQ
DM
DI n = Data in for column n Burst length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following Data In EN AP = Enable Autoprecharge * = * " Don't Care", if AP is high at this point ACT=Active, RA=Row Address, BA=Bank Address NOP commands are shown for ease of illustration; other valid commands may be possible at these times
Don't care
Rev. 0.1 / Jan. 2005
49
HY5DU283222AQP
Bank Write Access
tCK tCH tCL
/CK CK
tIS tIH
CKE
CMD
NOP
ACT tIS tIH RA
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
PRE
RA, CA
Col n
RA
RA tIS tIH All Banks
AP
tIS
RA tIH DIS AP One bank
BA0,BA1
Bank x tRCD
Bank x tRAS tDPL tDSH tDQSS tDQSH tWPST
Bank x
Case 1 : tDQSS = min DQS
tWPRES
tDQSL tWPRE
DQ
DI n
DM
Case 2 : tDQSS = max
tDSS tDQSS tDQSH
tDSS tWPST
DQS
tWPRES tWPRE DI n tDQSL
DQ
DM
DI n = Data in for column n Burst length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following Data In DIS AP = Disable Autoprecharge * = * " Don't Care", if AP is high at this point PRE=Precharge, ACT=Active, RA=Row Address NOP commands are shown for ease of illustration; other valid commands may be possible at these times
Don't care
Rev. 0.1 / Jan. 2005
50
HY5DU283222AQP
Write DM Operation
tCK tCH tCL
/CK CK
tIS tIH VALID
CKE
CMD
NOP
WRITE tIS tIH
NOP
NOP
NOP
NOP
PRE
NOP
NOP
ACT
RA, CA
Col n
RA
RA
tIS tIH All Banks
RA
AP
DIS AP tIS tIH One Bank
RA
BA0,BA1 Case 1 : tDQSS = min DQS
Bank x tDSH tDQSS tDQSH tWPST tDPL
Bank x tRP
BA
tWPRES tDQSL tWPRE
DQ
DI n
DM
Case 2 : tDQSS = max
tDSS tDQSS tDSS tDQSH tWPST
DQS
tWPRES tWPRE DI n tDQSL
DQ
DM
Don't care DI n = Data in for column n Burst length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following Data In (the second element of the four is masked) DIS AP = Enable Autoprecharge * = * " Don't Care", if AP is high at this point PRE=Precharge, ACT=Active, RA=Row Address, BA=Bank Address NOP commands are shown for ease of illustration; other valid commands may be possible at these times
Rev. 0.1 / Jan. 2005
51

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